From: Matthias Kruk <m@m10k.eu>
Date: Wed, 25 Sep 2019 08:07:48 +0000 (+0900)
Subject: Update the ESP0 and SS0 TSS entries when switching tasks
X-Git-Url: https://git.corax.cc/?a=commitdiff_plain;h=da02d4c77027c4592ce65ae8297ec853e4a37e20;p=corax

Update the ESP0 and SS0 TSS entries when switching tasks
---

diff --git a/kernel/arch/task.S b/kernel/arch/task.S
index 9f6a190..513c8a2 100644
--- a/kernel/arch/task.S
+++ b/kernel/arch/task.S
@@ -163,6 +163,23 @@ task_switch:
 	movl	$-1, %eax
 	ret
 
+	/* put the task's ESP0 into the TSS */
+	movl	OFFSET_ESP0(%edi), %ecx
+	movl	%ecx, CPU_ESP0(%eax)
+	movl	$KERNEL_DATA, CPU_SS0(%eax)
+
+	/*
+	 * We need to figure out the task's privilege level and
+	 * set the segment registers accordingly
+	 */
+	/*
+	movl	$KERNEL_CODE, CPU_CS(%eax)
+	movl	$KERNEL_DATA, CPU_DS(%eax)
+	movl	$KERNEL_DATA, CPU_ES(%eax)
+	movl	$KERNEL_DATA, CPU_FS(%eax)
+	movl	$KERNEL_DATA, CPU_GS(%eax)
+	*/
+
 2:	movl	OFFSET_CR3(%edi), %ecx
 
 	/* check if we can avoid writing to cr3, which would clear the TLB */