Fix a bug in task_switch() that would cause the TSS update to be skipped

diff --git a/kernel/arch/task.S b/kernel/arch/task.S
index 513c8a257d9a22f05f9e0255a99cb39e7714b5bf..b78b2af169a78fb3d6681c267c860efd63bb618b 100644 (file)
--- a/kernel/arch/task.S
+++ b/kernel/arch/task.S
@@ -36,7 +36,7 @@
 task_prepare:
        /*
         * int task_prepare(struct task*, u32_t cr3, u32_t eip,
-        *                  u32_t esp, u32_t priv)
+        *                  u32_t esp0, u32_t esp, u32_t priv)
         *
         *  priv  = 24(%esp)
         *  esp   = 20(%esp)
@@ -164,7 +164,7 @@ task_switch:
        ret
 
        /* put the task's ESP0 into the TSS */
-       movl    OFFSET_ESP0(%edi), %ecx
+2:     movl    OFFSET_ESP0(%edi), %ecx
        movl    %ecx, CPU_ESP0(%eax)
        movl    $KERNEL_DATA, CPU_SS0(%eax)
 
@@ -173,14 +173,14 @@ task_switch:
         * set the segment registers accordingly
         */
        /*
-       movl    $KERNEL_CODE, CPU_CS(%eax)
-       movl    $KERNEL_DATA, CPU_DS(%eax)
-       movl    $KERNEL_DATA, CPU_ES(%eax)
-       movl    $KERNEL_DATA, CPU_FS(%eax)
-       movl    $KERNEL_DATA, CPU_GS(%eax)
+       movl    $USER_CODE, CPU_CS(%eax)
+       movl    $USER_DATA, CPU_DS(%eax)
+       movl    $USER_DATA, CPU_ES(%eax)
+       movl    $USER_DATA, CPU_FS(%eax)
+       movl    $USER_DATA, CPU_GS(%eax)
+       movl    $USER_DATA, CPU_SS(%eax)
        */
-
-2:     movl    OFFSET_CR3(%edi), %ecx
+       movl    OFFSET_CR3(%edi), %ecx
 
        /* check if we can avoid writing to cr3, which would clear the TLB */
        movl    %cr3, %edx