extern struct cpu _cpu[CONFIG_SMP_CPUS];
struct memory_map *mmap;
u64_t mem_size;
+ u64_t i;
u32_t cr3;
- u32_t i;
-
- /* TODO: Clean up a little in here... */
_mem_start = (u32_t)&_mem_start + sizeof(u32_t);
mmap = (struct memory_map*)info->mmap_addr;
}
}
+#if FEATURE(DEBUG)
dbg_printf("Last usable address: 0x%016llx\n", mem_size);
dbg_printf("Allocating %lluKB for the frame set\n", (mem_size >> 15) / 1024);
+#endif /* FEATURE(DEBUG) */
/* FIXME: memory size is not good evidence of PAE capability */
if(mem_size < 0x100000000L) {
_frame_set(i);
}
- /* allpocate the proper page directory type for the kernel */
+ /* allocate the proper page directory type for the kernel */
switch(_pg_flags & PG_MODE_MASK) {
case PG_MODE_LEGACY:
cr3 = (u32_t)_phys_alloc(sizeof(page_table_t), PAGE_ALIGN);
u32_t attrs;
u64_t addr;
-#if 1
+#if FEATURE(DEBUG)
dbg_printf("Region: 0x%016llx - 0x%016llx [%u]\n",
mmap->addr, mmap->addr + mmap->len, mmap->type);
-#endif
+#endif /* FEATURE(DEBUG) */
+
/* FIXME: Memory in the region 0x100000:&_mem_start should NOT be writable! */
attrs = PAGE_ATTR_SIZE | PAGE_ATTR_WRITABLE | PAGE_ATTR_PRESENT;
break;
}
+
case PG_MODE_PAE: {
pdpt_t *pd;
}
break;
}
+
case PG_MODE_INTEL64:
case PG_MODE_IA32E:
PANIC("How did I get here?");
_kernel_pgdir->pd_regions[REGION_TEXT].reg_pgsize = PAGE_SIZE;
_kernel_pgdir->pd_regions[REGION_TEXT].reg_attrs = PAGE_ATTR_PRESENT | PAGE_ATTR_USER;
- _kernel_pgdir->pd_regions[REGION_HEAP].reg_base = (void*)ALIGN((u32_t)&_mem_start, PAGE_SIZE);
- _kernel_pgdir->pd_regions[REGION_HEAP].reg_size = ALIGN(_mem_start + CONFIG_KERNEL_HEAP_SIZE, PAGE_SIZE);
+ /* what about the area between &_mem_start and _mem_start? */
+
+ _kernel_pgdir->pd_regions[REGION_HEAP].reg_base = (void*)ALIGN((u32_t)_mem_start, PAGE_SIZE);
+ _kernel_pgdir->pd_regions[REGION_HEAP].reg_size = ALIGN(CONFIG_KERNEL_HEAP_SIZE, PAGE_SIZE);
_kernel_pgdir->pd_regions[REGION_HEAP].reg_pgsize = PAGE_SIZE;
_kernel_pgdir->pd_regions[REGION_HEAP].reg_attrs = PAGE_ATTR_PRESENT | PAGE_ATTR_WRITABLE;